1. Field of the Invention
The present invention generally relates to circuits that provide electrostatic discharge protection, and more particularly, to a method and apparatus for protecting a gate oxide using source/bulk pumping.
2. Description of the Background Art
The protection of an ultra-thin gate oxide against electrostatic discharge (ESD) stress is a critical factor in obtaining sufficiently high levels of ESD hardness in advanced CMOS technologies. When the voltage applied to a gate oxide becomes too high, the gate oxide will suffer from catastrophic damage, i.e., it will break down. Typically, SiO2 breaks down at electric field strengths of 6-9 MV/cm (DC). During ESD stress, the pulse duration is typically on the order of 100 ns, allowing significantly higher voltage across the oxide before damage occurs, i.e., the maximum field that causes breakdown may be about 20 MV/cm. Conventional ESD protection circuits, e.g., ESD clamps, work well at protecting standard, circuits.
When a gate oxide is about or thinner than 5 nm, an ESD event causes a quantum-mechanical tunneling effect and electrons will pass through the oxide creating a tunneling current. Such a tunneling current leads to excessive power dissipation. The gate oxide very quickly suffers overheating and is irreversibly damaged. Damage can occur in the following regions of the gate oxide: directly between the gate electrode and the substrate (bulk) and/or between the gate facing either the source or the drain region. In typical dual-well CMOS technologies (where the P-well is not isolated from the substrate), the gate-to-bulk oxide breakdown occurs at significantly higher voltage levels as compared to the gate-to-source/drain breakdown. For example, an ultra-thin gate oxide has been found to have a gate-to-source breakdown voltage, BVox(G-S), of approximately 5V. On the other hand, the gate-to-bulk breakdown voltage, BVox(G-B), for the same device, occurs at a higher voltage, e.g., greater than 10V. Consequently, to protect an ultra-thin gate oxide designers have predominantly focused on limiting the more critical gate-to-source ESD voltage.
FIG. 1 depicts a graph 100 of an example of a transient breakdown characteristic for a transistor with a gate oxide thickness of 2.2 nm. As depicted in plot 102 of gate current versus applied gate-to-source voltage, excessive tunneling current begins at around 6V and damage occurs at around 7V. Overlaid, to form a so-called “ESD Design Window”, is a plot 104 of the I-V characteristic of a prior art ESD protection clamp (e.g., GGNMOS). A comparison of the I-V characteristic of the ESD protection device (plot 104) with the breakdown characteristic of the ultra-thin gate oxide (plot 102) demonstrates that the voltage across the clamp quickly exceeds the tunneling voltage and the breakdown voltage of the oxide. Thus, the capability of the protection device (i.e., to clamp the ESD voltage transient) is rather limited. Consequently, the use of a traditional ESD protection device with ultra-thin gate oxide devices has limited effectiveness in protecting the devices from gate damage from ESD events.
Technology downscaling forces the oxide thickness to decrease further and further, while the I-V characteristics for clamping devices do not scale down at the same pace because of certain physical limitations to scaling the protection circuits. As the continued reduction of oxide thickness further reduces the breakdown voltage to lower and lower values, the ESD protection device cannot effectively protect the oxide by clamping the voltage. As depicted in FIG. 1, the ineffectiveness becomes obvious in a reduced maximum ESD stress handling current Imax (in contrast to the actual limit of the clamp as determined by its second breakdown trigger current It2). As such, the value of using conventional ESD protection devices with ultra-thin gate oxide devices is limited.
Therefore, there is a need in the art for a method and apparatus for protecting ultra-thin gate oxides from damage during an ESD event.